The semiconductor industry is increasingly being driven to decrease the size of semiconductor devices located on integrated circuits. For example, miniaturization is needed to accommodate the increasing density of circuits necessary for today's semiconductor products. Increased packing density and device size reduction has forced semiconductor device structures such as transistors to be located ever closer to one another. Because of the close proximity of adjacent transistors, methods have been developed to place electrical isolation structures between adjacent transistors. Several techniques or isolation processes have been employed to provide the requisite isolation in integrated semiconductor devices.
One such process is the local oxidation of silicon (LOCOS). In LOCOS, a thermally grown SiO2 pad separates adjacent devices (e.g., PMOS and NMOS transistors in CMOS structure). Local oxidation is accomplished using silicon nitride (Si3N4) to prevent oxidation of silicon in selected areas. The Si3N4 may then be etched off following thermal oxidation. The LOCOS process has been used widely as an isolation technique for very large-scale integrated (VLSI) circuits. Unfortunately, LOCOS isolation processes have encountered limitations in smaller sub-micron technologies due to the well-known “bird's beak” that reduces the packing density.
An alternative isolation technique or process known as shallow trench isolation (STI) has been developed to provide electrical isolation between adjacent CMOS transistors. In STI, a shallow trench having a depth of around 2500 Å is created. The shallow trench is then filled by thermal oxidation. Unfortunately, the filling process creates a non-planar surface that requires chemical mechanical polishing (CMP) to planarize the resulting structure. The conventional STI process thus involves one mask level, one gas phase etching step, one oxidation step, and one CMP step. The cross-sectional profile of the oxide is generally controlled by the dry etching conditions.
Regardless of the process used, the isolation structure that is created is characterized by its isolation effectiveness between the source and drain regions between neighboring transistors as well as between the source and drain of the same transistor (when turned off). Important metrics for the effectiveness of a particular isolation structure include the highest voltage the structure can withstand before significant current flow, the source-to-drain leakage when the transistor is in the “off” state, and the severity of the short channel effect.
As stated above, conventional STI processes include a CMP planarization step. Unfortunately, CMP processes are generally expensive and often introduce a number of yield-limiting defects. These include residual slurry, surface voids, and surface particles. Microscratches may also form if a small particle or other debris is caught between the polishing pad and the surface of the substrate during polishing.
There thus is a need for a STI-based process that does not require a CMP planarization step. The process would be able to form a perfect or near-perfect planar topography on the substrate comparable to that provided by CMP-based processes. In addition, there is a need for an alternative process for fabricating STI structures that offer the ability to tailor the cross-sectional profile of the trenches for improved electronic properties.